The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a structure and method for a high performance electronic packaging assembly.
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever increasing number of linked transistors. As the number of transistors required increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and on different wafers or chips. It is an objective in the semiconductor industry to construct transistors which occupy less surface area on the silicon chip/die.
As integrated circuit technology progresses there is a growing desire for a xe2x80x9csystem on a chip.xe2x80x9d Ideally, a computing system would be fabricated with all the necessary integrated circuits on one wafer, as compared with today""s method of fabricating many chips of different functions and packaging them to assemble a complete system. Such a structure would greatly improve integrated circuit performance and provide higher bandwidth. In practice, it is very difficult with today""s technology to implement a truly high-performance xe2x80x9csystem on a chipxe2x80x9d because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits. Thus, what is needed is an improved method and structure which continues to approach the ideal set-up of a xe2x80x9csystem on a chipxe2x80x9d and thus improves the integration of different chips in an integrated circuit.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop a structure and method to increase the operational speeds, or data bandwidth, between different circuit devices, e.g. logic and memory chips. It is further desirable to attain this ability using current CMOS fabrication techniques.
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method are provided to maximize the bandwith between different circuit devices.
In particular, an illustrative embodiment of the present invention includes an electronic packaging assembly. The electronic packaging assembly includes a silicon interposer which has a first and second side. At least one semiconductor chip is located on a first side of the silicon interposer. At least one semiconductor chip is located on a second side of the silicon interposer. A number of electrical connections exist through the silicon interposer which couple the semiconductor chips located on each side of the silicon interposer.
In another embodiment, an electronic system module is provided. The electronic system module includes a silicon interposer which has opposing surfaces. A microprocessor is included which has a circuit side. The circuit side of the microprocessor faces a first one of the opposing surfaces of the silicon interposer. A first memory chip is included which has a circuit side. The circuit side of the memory chip faces a second one of the opposing surfaces of the silicon interposer. Further, a number of electrical connections are provided which extend through the silicon interposer. The number of electrical connections couple the circuit side of the microprocessor to the circuit side of the first memory chip.
In another embodiment, a computer system is provided. The computer system includes an electronic packaging assembly. The electronic packaging assembly includes the electronic packaging assembly presented and described above. A number of external devices are included. A system bus couples the electronic packaging assembly to the number of external devices.
In another embodiment, a method for forming integrated circuits is provided. The method includes providing a silicon interposer which has opposing sides. A first semiconductor chip is coupled to a first side of the silicon interposer. A second semiconductor chip is coupled to a second side of the silicon interposer. The method further includes coupling the first semiconductor chip to the second semiconductor chip by means of electrical connections through the silicon interposer.
In an alternative embodiment, a method for forming integrated circuit is provided. The method includes providing a silicon interposer which has opposing sides. A number of micro-machined vias are formed through the silicon interposer. The micro-machined vias include a number of electrical connections between the opposing surfaces of the silicon interposer. A logic chip is coupled to the number of micro-machined vias on a first side of the silicon interposer. The method further includes coupling a memory chip to the number of micro-machined vias on a second side of the silicon interposer.
Thus, an improved structure and method are provided. The structure and method increase the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. This provides the added advantage of low cost and availability. A silicon interposer is thermally matched to the circuit devices such that coefficient of expansion mismatches are nonexistent. And, deposition of conductors on the silicon interposer""s surface is readily accomplished using a standard integrated circuit multi-layer metallurgy.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.